Scientific publications

The use of mobile devices is often limited by the battery lifetime. Some devices have the option to connect an extra battery, or to use smart battery-packs with multiple cells to extend the lifetime. In these cases, scheduling the batteries or battery cells over the load to exploit the recovery properties of the batteries helps to extend the overall systems lifetime.

Modern multi-processor systems need to provide guaranteed services to their users. A communication assist (CA) helps in achieving tight timing guarantees. In this paper, we present a CAfor a tile-based MP-SoC. Our CA has smaller memory requirements and a lower latency than existing CAs. The CAhas been implemented in hardware.

Media processing systems often have limited resources and strict performance requirements. An implementation must meet those design constraints while minimizing resource usage and energy consumption. Design-space exploration techniques help system designers to pinpoint bottlenecks in a system for a given configuration.

The concept of Reference Architectures is novel in the business world. However, many architects active in the creation of complex systems frequently use the term Reference Architecture. Yet, these experienced architects do not collectively have a consistent notion of what constitutes a Reference Architecture, what is the value of maintaining the Reference Architecture, what is the best approach to visualizing a Reference Architecture, what is the most appropriate level of abstraction, and how should an architect make use of the Reference Architecture in their work? This paper examines current Reference Architectures and the driving forces behind development of them to come to a collective conclusion on what a Reference Architecture should truly be.

This paper proposes a framework for (signal) interconnect power optimization at the global routing stage. In a typical design flow, the primary objective of global routing is minimization of wirelength and via consumption. Our framework takes a global routing solution that is optimized for this objective, and quickly generates a new solution that is optimized for signal power, with only a small, controlled degradation in wirelength.

This paper presents a novel system-level analysis of soft error rates (SER) based on the Transaction Level Model (TLM) of a targeted System-On-a-Chip (SoC). This analysis runs 1000x faster than the conventional SoC analysis using a gate-level model. Moreover, it allows accurate prediction in the early design phase of a SoC, when only limited application details are available.

POOSL (Parallel Object-Oriented Specification Language) is a powerful general purpose system-level modeling language. In research on design space exploration of motion control systems, POOSL has been used to construct models for performance analysis. The considered motion control algorithms are characterized by periodic execution.

Control software is an integral part of new complex electromechanical systems, such as professional high speed printers. The development of these multidisciplinary products involves a number of iterative and incremental cycles of prototype creation. Automatically generating control software is a big leap in rapid prototyping of these products.

Packet switched networks are widely used for interconnecting distributed computing platforms. RapidIO (Rapid Input/Output) is an industry standard for packet switched networks to interconnect multiple processor boards. Key performance metrics for these platforms include average-case and worst-case packet transfer latencies.

The design of new embedded systems is getting more and more complex as more functionality is integrated into these systems. To deal with the design complexity, a predictable design flow is needed. The result should be a system that guarantees that an application can perform its own tasks within strict timing deadlines, independent of other applications running on the system.